Memory buffer having accessible information after a program-fail

ABSTRACT

A memory device, and a method of operating same, utilize a first memory buffer associated with a first memory array and a second memory buffer associated with a second memory array to maintain information subsequent to a program-fail event associated with the first memory array and to provide the information to the second memory array.

BACKGROUND

1. Field

Subject matter disclosed herein relates to a memory device, and a methodof operating same.

2. Information

Memory devices are employed in many types of electronic devices, such ascomputers, cell phones, PDA's, data loggers, and navigational equipment,just to name a few examples. Among such electronic devices, varioustypes of nonvolatile memory devices may be employed, such as NAND or NORflash memories, SRAM, DRAM, and phase-change memory, just to name a fewexamples. In general, writing or programming processes may be used tostore information in such memory devices, while a read process may beused to retrieve stored information.

Occasionally during operation of a memory device, a process of writingand/or reading information to/from a memory array may fail. Such afailure need not necessarily lead to a fatal operational error if amemory device includes safeguards such as error correction and/or anability to re-initiate a read and/or write process, for example. Havingsuch safeguards, however, may result in extra costs such as a use of amemory device area that could otherwise be used for other purposesand/or adding steps to a process to fabricate the memory device, forexample.

BRIEF DESCRIPTION OF THE FIGURES

Non-limiting and non-exhaustive embodiments will be described withreference to the following figures, wherein like reference numeralsrefer to like parts throughout the various figures unless otherwisespecified.

FIG. 1 is a schematic block diagram of a memory device, according to anembodiment.

FIG. 2 is a schematic block diagram of a memory device, according toanother embodiment.

FIG. 3 is a flow diagram of a process to program a memory device,according to an embodiment.

FIG. 4 is a flow diagram of a process to program a memory device,according to another embodiment.

FIG. 5 is a schematic block diagram of a computing system and a memorydevice, according to an embodiment.

DETAILED DESCRIPTION

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of claimed subject matter. Thus, theappearances of the phrase “in one embodiment” or “an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in one or moreembodiments.

In an embodiment, a memory device may comprise a memory controller toinitiate a program operation to write particular information to a memoryarray. Such a memory device may also comprise a memory buffer to receivethe particular information from the memory controller, to store theparticular information during the program operation, and to store theparticular information subsequent to a program-fail event. Such aprogram-fail event may result from any of a number of situations, suchas defects of one or more memory cells, memory blocks, or other portionof a memory array, for example. Such defects may arise from afabrication process or may result from physical changes subsequent tothe fabrication of a memory device. For example, one or more defectivememory cells in a memory block may result in the entire memory blockbeing defective. Such a bad memory block may lead to a failure to readfrom or write to the bad memory block. Accordingly, a memory buffer thatmaintains particular information subsequent to such a write failure mayhave such particular information available to a subsequent re-writeprocess. Of course, such reasons for program-fail events are merelyexamples, and claimed subject matter is not so limited.

In other words, such a memory buffer may maintain stored informationafter such information failed to be successfully written from the memorybuffer to a memory array. In a particular implementation, for example,such a memory buffer may comprise a NAND page buffer, though otherparticular memory types may be used in other implementations. As aresult of maintaining information or data during a program-fail event, adata page, for example, may still be available to a NAND user (e.g., amemory card controller) after a failure to program such a data page intoa block of a NAND memory array. Accordingly, such a data page, stillpresent in a NAND page buffer, may be accessible for reading, modifying,and/or re-programming into another block of memory array.

In an embodiment, information being programmed may be present in a NANDpage buffer during a program-busy portion of a write operation. Suchinformation may be additionally available for further reading and/ormodifying or rewriting using a read-from-buffer command and/or awrite-from-buffer command if a program-fail event affects pageprogramming, due, for example, to a bad memory block. An embodiment ofsuch a memory device as described above, for example, may provide anumber of benefits including a memory architecture that avoids usingmemory die area for an additional controller RAM buffer to maintaininformation in case such information fails to be successfully programmedin a memory array. In an implementation, a NAND page buffer may be usedas additional volatile memory in a particular operation, for example,that need not use non-volatile data storage. Of course, such benefits ofembodiments described herein are merely examples, and claimed subjectmatter is not so limited.

Embodiments, such as those described above, may allow implementation ofa relatively robust bad-block management that hides internal bad memoryblocks from an external host. Such bad-block management may operateusing spare memory blocks or other memory portions to substitute for badblocks. In one implementation, a process of hiding bad memory blocks maymean that no error information would be returned to a host other than,for example, an “operation complete” message after related operationsare completed. For example, a memory device may receive a write and/orerase command from a host. If such a write and/or erase operation leadsto an internal bad block generation, then a memory controller of thememory device may manage internally remap/recopy processes in order tocarry out the write and/or erase operation. Such management may betransparent to the host, which may merely receive an indication that awrite and/or erase operation is completed. In one implementation, suchmanagement may involve holding a pending programming page in an extracontroller random access memory (RAM) in order to repeat a new pageprogram onto another “fresh” block if a fail of a first block occurs.However, such extra RAM may occupy valuable area on a memory die thatmay otherwise be used for another purpose. For example, extra controllerRAM may use about a square millimeter for 0.11 micron technology. Inanother implementation, such management may involve an error correctingcode (ECC) engine and a process to read back (for recopy) a just-failedpage directly from a NAND block, instead of holding original informationinto an extra RAM buffer. Success of such an implementation may rely onan ease with which damage that occurred during a programming phase maybe corrected using ECC. However, it may be more likely that such damagethat occurred after a page program fail is not correctable by ECC due toperformance limitations of the ECC. Of course, such an implementation ofan ECC is merely an example, and claimed subject matter is not solimited.

FIG. 1 is a schematic block diagram of a memory device 110, according toan embodiment. Such a memory device 110 may receive information and/orinstructions 115 from an external host (not shown). Subsequent to aprogram-fail event, memory device 110 may be capable of repeatingattempts to re-program information to nonvolatile memory, as describedin detail below. However, such a capability may include a cost of havingan additional controller RAM buffer to maintain information for suchre-programming attempts, as also described below. Arrows in FIGS. 1-3are single-ended to correspond to descriptions of particular embodimentsand implementations that follow. However, any or all such arrows may bedouble-ended to indicated flow in either one or both directions, andclaimed subject matter is not limited in this respect. For example,arrow 115 may represent information provided to memory device 110 and/orinformation provided by memory device 110 to an external entity.

In a particular implementation, memory device 110 may comprise a NANDflash memory card usable by a number of types of hosts to storeinformation. For example memory device 110 may comprise a memory cardused for a digital camera (the host), a “thumb drive”, and so on. In anembodiment, memory device 110 may comprise a controller 150 and a memoryportion 160. Further, controller 150 may comprise controller RAM bufferinterface 120 and a processor 130 that may include an ECC engine 135.Memory portion 160 may comprise one or more memory partitions 155 and165, for example. Such memory partitions may be on a same die or onseparate die, and claimed subject matter is not so limited. Individualmemory partition 155 may include internal RAM buffer 185 and memoryarray 195. Individual memory partition 165 may include internal RAMbuffer 170 and memory array 180. Although not shown, memory portion 160may include additional memory partitions. In one implementation, such aninternal RAM buffer may comprise a NAND page buffer. For example, RAMbuffer 185 and 170 may comprise a volatile memory to host a page ofinformation to be programmed to memory array 195 and memory array 180,respectively. Memory array 195 and memory array 180 may comprisenonvolatile memory.

Referring to memory device 110, in response to a program-fail event(e.g., bad block occurrence) during a write operation, informationpreviously written to a bad memory block may be copied to a new memoryblock. Information, in response to the program-fail event, may also becopied to the new memory block. In one implementation, memory device 110may return to a host a write-operation-complete signal, thus hiding fromthe host the program-fail event. Such a write process is now explainedin detail. A host (not shown) may provide information 115 to memorydevice 110 for writing to a nonvolatile portion of a memory array 180,for example. Such information 115 may be temporarily stored incontroller RAM buffer interface 120 and subsequently transferred toprocessor 130 via line 125. Processor 130 may next transfer information115 into RAM buffer 170 via line 140. Meanwhile, information 115 neednot be maintained in controller RAM buffer interface 120. RAM buffer170, via line 178, may transfer information 115 to memory array 180. Ifa program-fail event occurs during such a transfer of information tomemory array 180, then a process to retry programming may proceed asfollows. Information 115 that failed to be fully written into memoryarray 180 may be at least partially retrieved from the memory array andplaced in RAM buffer 170 using a read operation via line 175, forexample. Information 115 may be read from RAM buffer 170 via line 145 tobe processed by ECC engine 135 to correct one or more errors resultingfrom the program-fail event. If ECC engine 135 successfully correctssuch errors, information 115 may be copied to another memory array 195via line 153, RAM buffer 185, and line 190, for example. Accordingly,such a process of retrying programming may rely on the success of ECCengine 135. Of course, such details of a write process are merelyexamples, and claimed subject matter is not so limited.

FIG. 2 is a schematic block diagram of a memory device 210, according toan embodiment. Similar to memory device 110 shown in FIG. 1, forexample, memory device 210 may receive information and/or instructions215 from an external host (not shown). In a particular implementation,memory device 210 may comprise a NAND flash memory card that may beusable by a number of types of hosts to store information. For examplememory device 210 may comprise a memory card used for a digital camera(the host), a “thumb drive”, and so on. As for memory device 110, memorydevice 210 may be capable of repeating attempts to re-programinformation to nonvolatile memory subsequent to a program-fail event. Incontrast to memory device 110, however, such a capability of memorycontroller 210 may be provided by a RAM buffer located between a memorycontroller and a memory array to where such information is to beprogrammed, as also described below. For example, memory device 110included a controller RAM buffer to maintain information for suchre-programming attempts, whereas memory device 210 need not rely on sucha controller RAM buffer for re-programming.

In an implementation, memory device 210, similar to memory device 110,may comprise a controller 250 and a memory portion 260. Further,controller 250 may comprise controller RAM buffer interface 220 and aprocessor 230 including an ECC engine 235. Memory portion 260 maycomprise one or more memory partitions 255 and 265, for example. Suchmemory partitions may be on a same die or on separate die, and claimedsubject matter is not so limited. Individual memory partition 255 mayinclude internal RAM buffer 285 and memory array 295. Individual memorypartition 265 may include internal RAM buffer 270 and memory array 280.Although not shown, memory portion 260 may include additional memorypartitions. In one implementation, such an internal RAM buffer maycomprise a NAND page buffer. For example, RAM buffer 285 and 270 maycomprise a volatile memory to host a page of information to beprogrammed to memory array 295 and memory array 280, respectively.Memory array 295 and memory array 280 may comprise nonvolatile memory.

Referring to memory device 210, in response to a program-fail event(e.g., bad block occurrence) during a write operation, informationpreviously written to a bad memory block may be copied to a new memoryblock. Current information, in response to the program-fail event, mayalso be copied to the new memory block. In one implementation, memorydevice 210 may return to a host a write-operation-complete signal, thushiding from the host the program-fail event. Such a write process is nowexplained in detail. A host (not shown) may provide information 215 tomemory device 210 for writing to a memory array 280, for example. Suchinformation 215 may be temporarily stored in controller RAM bufferinterface 220 and subsequently transferred to processor 230 via line225. Processor 230 may next transfer information 215 into RAM buffer 270via line 240. In one implementation, similar to memory device 110,controller RAM buffer interface 220 may be cleared of information 215subsequent to transfer of information 215 to RAM buffer 270. RAM buffer270, via line 278, may transfer information 215 to memory array 280. Ifa program-fail event occurs during such a transfer of information tomemory array 280, then a process to retry programming may proceed asfollows. Information 215 that failed to be written into memory array 280may still be maintained in RAM buffer 270. Accordingly, such maintainedinformation may be available for another program operation to anotherportion of memory in memory array 280 via line 275, for example. Such anadditional program operation using information maintained in RAM buffer270 may occur in response to a write-from-buffer command initiated byprocessor 230.

In another embodiment, after a program-fail event, informationmaintained in RAM buffer 270 may be available for another programoperation to another memory array 295. Such an additional programoperation using information maintained in RAM buffer 270 may occur inresponse to a read-from-buffer command initiated by processor 230. Indetail, information 215 that failed to be written into memory array 280may be retrieved from RAM buffer 270 after such a failure of a programoperation using the read-from-buffer command operation. In oneimplementation, information 215 may be read from RAM buffer 270 via line245. Information 215 may be written to another memory array 295 via line253, RAM buffer 285, and line 290, for example. In anotherimplementation, information 215 may be read from RAM buffer 270 via line245 to processor 230, which may determine another memory location towhere information 215 is to be written during a re-program process. Forexample, such a memory location may comprise memory array 295, which maybe located on a same or different die as that of memory array 280 wherethe program-fail occurred.

FIG. 3 is a flow diagram of a process 300 to program a memory device,according to an embodiment. At block 310, a host of a memory device,such as camera, a cell phone, or other electronic device havinginformation to store, may provide such information to a memorycontroller of the memory device. At block 320, such information may bewritten to a memory buffer. In one implementation, a memory buffer maycomprise a RAM page buffer, for example. At block 330, during a programoperation that writes information from the memory buffer to a memoryarray, the memory buffer may provide a signal to the memory controllerto indicate that the memory buffer is busy. At block 340, informationstored in the memory buffer during the program operation that writesinformation to the memory array may be maintained subsequent to theprogram operation. Such a program operation may either succeed or fail,and a determination of either possibility may be performed at block 350.In one implementation, such a determination of whether a program-failevent has occurred may be performed by the memory controller subsequentto de-assertion of a NAND program busy signal. At this time, the memorycontroller may check a NAND status register containing a result (e.g.,success or failure) of the operation. At block 360, in the case of asuccessful program operation, the memory device may provide a signal tothe host of the memory device indicating that the program operation wassuccessful and/or is complete. Otherwise, at block 370, in the case of aprogram-fail event, a memory controller may issue a write-from-buffercommand to the memory buffer. Accordingly, at block 380, subsequent to afailed program operation, information maintained by a memory buffer maybe written to a memory array. Such a memory array may comprise the samememory array as that involved with the earlier failed program operation.Optionally, information maintained by a memory buffer may be written toa different memory array. If the memory array is the same as thatinvolved with the failed program operation, then a different portion ofthe memory array may be used in the process of block 380. For example,such a different portion of the memory array may comprise a differentblock of the memory array. In one implementation, the memory controllerof the memory device may determine such memory locations to writeinformation during a re-program process. As mentioned above, informationmay be written to a memory location of a memory array located on a diethat is different from that of the memory array involved in theprogram-fail event. Finally, process 300 may proceed to block 360, wherethe memory device may provide a signal to the host of the memory deviceindicating that the program operation was successful and/or is complete.In such a case, the occurrence of a program-fail event may be hiddenfrom the host, as discussed above.

FIG. 4 is a flow diagram of a process 400 to program a memory device,according to an embodiment. At block 410, a host of a memory devicehaving information to store may provide such information to a memorycontroller of the memory device. At block 420, the information may bewritten to a memory buffer. In one implementation, such a memory buffermay comprise a RAM page buffer, for example. At block 430, during aprogram operation to write information from the memory buffer to amemory array, the memory buffer may provide a signal to the memorycontroller indicating that the memory buffer is busy. At block 440,information may be stored in a memory buffer during a program operationto write such information to a memory array. Additionally, suchinformation may be maintained in a memory buffer subsequent to a programoperation. Such a program operation may either be successful or fail,and a determination of either event may be performed at block 450. Atblock 460, in the case of a successful program operation, a memorydevice may provide a signal to the host of the memory device to indicatethat the program operation was successful and/or is complete. Otherwise,at block 470, in the case of a program-fail event, the memory controllermay issue a read-from-buffer command to the memory buffer. Accordingly,information maintained by the memory buffer subsequent to the attemptedand failed program operation may be read from the memory buffer. In oneimplementation, however, such read information may be provided to thememory controller that may determine a portion of memory, other than theportion of memory involved in the program-fail event, in which to storethe information retrieved from the memory buffer. Similarly, at block480, information read from the memory buffer may be written to a portionof memory that has not previously led to a program-fail event. Forexample, such a portion of memory may comprise a block and/or a page ofmemory that is different from a block and/or a page of memory that ledto a previous program-fail event. As mentioned above, information may bewritten to a memory location of a memory array located on a die that isdifferent than that of the memory array involved in the program-failevent. Finally, process 400 may proceed to block 460, where the memorydevice may provide a signal to the host of the memory device indicatingthat the program operation was successful and/or is complete. In such acase, the occurrence of a program-fail event may be hidden from thehost, as discussed above.

FIG. 5 is a schematic view of a computing system 500 and a memorydevice, according to an embodiment. Such a computing device may compriseone or more processors, for example, to execute an application and/orother code. For example, memory device 510 may comprise a memory array280 shown in FIG. 2. A computing device 504 may be representative of anydevice, appliance, or machine that may be configurable to manage memorydevice 510. Memory device 510 may include a memory controller 515 and amemory 522. In one implementation, such a memory device may comprisememory device 210, controller 250, and memory 280 shown in FIG. 2, forexample. By way of example but not limitation, computing device 504 mayinclude: one or more computing devices and/or platforms, such as, e.g.,a desktop computer, a laptop computer, a workstation, a server device,or the like; one or more personal computing or communication devices orappliances, such as, e.g., a personal digital assistant, mobilecommunication device, or the like; a computing system and/or associatedservice provider capability, such as, e.g., a database or data storageservice provider/system; and/or any combination thereof.

It is recognized that all or part of the various devices shown in system500, and the processes and methods as further described herein, may beimplemented using or otherwise including hardware, firmware, software,or any combination thereof. Thus, by way of example but not limitation,computing device 504 may include at least one processing unit 520 thatis operatively coupled to memory 522 through a bus 540 and a host ormemory controller 515. Processing unit 520 is representative of one ormore circuits configurable to perform at least a portion of a datacomputing procedure or process. By way of example but not limitation,processing unit 520 may include one or more processors, controllers,microprocessors, microcontrollers, application specific integratedcircuits, digital signal processors, programmable logic devices, fieldprogrammable gate arrays, and the like, or any combination thereof.Processing unit 520 may include an operating system configured tocommunicate with memory controller 515. Such an operating system may,for example, generate commands to be sent to memory controller 515 overbus 540. Such commands may comprise read and/or write commands. Inresponse to a write command, for example, memory controller 515 mayprovide a bias signal, such as a set or reset pulse to write informationassociated with the write command to a memory partition, for example.

Memory 522 is representative of any data storage mechanism. Memory 522may receive information to be stored via RAM buffer 570, which may besimilar to RAM buffer 270 shown in FIG. 2, for example. Memory 522 mayinclude, for example, a primary memory 524 and/or a secondary memory526, each of which may be partitioned into one or more partitions asdiscussed above, for example. Primary memory 524 may include, forexample, a random access memory, read only memory, etc. Whileillustrated in this example as being separate from processing unit 520,it should be understood that all or part of primary memory 524 may beprovided within or otherwise co-located/coupled with processing unit520.

Secondary memory 526 may include, for example, the same or similar typeof memory as primary memory and/or one or more data storage devices orsystems, such as, for example, a disk drive, an optical disc drive, atape drive, a solid state memory drive, etc. In certain implementations,secondary memory 526 may be operatively receptive of, or otherwiseconfigurable to couple to, a computer-readable medium 528.Computer-readable medium 528 may include, for example, any medium thatcan carry and/or make accessible data, code, and/or instructions for oneor more of the devices in system 500.

In one embodiment, system 500 may comprise a memory device, such asmemory device 200 shown in FIG. 2, for example. Such a memory device maycomprise a memory controller 515 to initiate a program operation towrite particular information to a memory array. The memory device mayalso comprise a memory buffer 570 to receive the particular informationfrom the memory controller, to store the particular information duringthe program operation, and to store the particular informationsubsequent to a program-fail event. System 500 may further comprise aprocessor 520 to host one or more applications and to initiate writecommands to the memory controller to provide access to said memoryarray. In one implementation, the memory buffer may comprise a NAND pagebuffer internal to a NAND memory comprising the memory array.

Computing device 504 may include, for example, an input/output 532.Input/output 532 is representative of one or more devices or featuresthat may be configurable to accept or otherwise introduce human and/ormachine inputs, and/or one or more devices or features that may beconfigurable to deliver or otherwise provide for human and/or machineoutputs. By way of example but not limitation, input/output device 532may include an operatively configured display, speaker, keyboard, mouse,trackball, touch screen, data port, etc.

While there has been illustrated and described what are presentlyconsidered to be example embodiments, it will be understood by thoseskilled in the art that various other modifications may be made, andequivalents may be substituted, without departing from claimed subjectmatter. Additionally, many modifications may be made to adapt aparticular situation to the teachings of claimed subject matter withoutdeparting from the central concept described herein. Therefore, it isintended that claimed subject matter not be limited to the particularembodiments disclosed, but that such claimed subject matter may alsoinclude all embodiments falling within the scope of the appended claims,and equivalents thereof.

What is claimed is:
 1. A method comprising: initiating a programoperation to write particular information to a first memory array via afirst memory buffer; maintaining said particular information in saidfirst memory buffer subsequent to a program-fail event; and subsequentto said program-fail event, writing said particular information to asecond memory buffer associated with a second memory array.
 2. Themethod of claim 1, further comprising: determining said program-failevent during said program operation; retrieving said particularinformation from said first memory buffer; and writing said particularinformation to the second memory array via the second memory buffer. 3.The method of claim 1, wherein said first memory buffer comprises a NANDpage buffer.
 4. The method of claim 1, wherein a memory device comprisesa first memory partition and a second memory partition, said firstmemory partition comprising said first memory array and said firstmemory buffer, and said second memory partition comprising said secondmemory array and said second memory buffer, wherein said memory devicecomprises a NAND-based memory card to receive said particularinformation from a memory card controller.
 5. The method of claim 1,further comprising, subsequent to said program-fail event, instructingsaid first memory buffer to write said particular information from saidfirst memory buffer to said first memory array.
 6. The method of claim1, further comprising, subsequent to said program-fail event, readingsaid particular information stored in said first memory buffer.
 7. Amemory device comprising: a memory controller to initiate a programoperation to write particular information to a memory array; a firstmemory buffer associated with a first portion of said memory array; anda second memory buffer associated with a second portion of said memoryarray, wherein said first memory buffer is configured to receive saidparticular information from said memory controller, to store saidparticular information during said program operation, and to store saidparticular information subsequent to a program-fail event associatedwith the first portion of said memory array, wherein the first portionof said memory array receives said particular information from saidmemory controller via said first memory buffer and, subsequent to saidprogram-fail event, the particular information is written to the secondmemory bufer and the second portion of said memory array receives saidparticular information via said second memory buffer.
 8. The memorydevice of claim 7, wherein said first memory buffer comprises a NANDpage buffer.
 9. The memory device of claim 7, wherein said first memorybuffer and the first portion of said memory array are disposed on a samedie.
 10. The memory device of claim 7, wherein said memory devicecomprises a NAND-based memory card to receive said particularinformation from a memory card controller.
 11. The memory device ofclaim 7, wherein said memory controller, in response to saidprogram-fail event, is further configured to instruct said first memorybuffer to write said particular information from said first memorybuffer to the first portion of said memory array.
 12. The memory deviceof claim 7, wherein said memory controller, in response to saidprogram-fail event, is further capable of reading said particularinformation stored in said first memory buffer.
 13. The memory device ofclaim 12, wherein said memory controller, subsequent to said reading, isfurther capable of providing said particular information to said secondmemory buffer associated with the second portion of said memory array.14. A system comprising: a memory device comprising: a memory controllerto initiate a program operation to write particular information to amemory array; a first memory buffer associated with a first portion ofsaid memory array; a second memory buffer associated with a secondportion of said memory array, wherein said first memory buffer isconfigured to receive said particular information from said memorycontroller, to store said particular information during said programoperation, and to store said particular information subsequent to aprogram-fail event associated with the first portion of said memoryarray, wherein the first portion of said memory array receives saidparticular information from said memory controller via said first memorybuffer and subsequent to said program-fail event, the particularinformation is written to the second memory buffer and the secondportion of said memory array receives said particular information viasaid second memory buffer; and a processor to host one or moreapplications and to initiate write commands to said memory controller toprovide access to said memory array.
 15. The system of claim 14, whereinsaid first memory buffer comprises a NAND page buffer internal to a NANDmemory comprising said memory array.
 16. The system of claim 14, whereinsaid first memory buffer comprises a volatile memory.
 17. The system ofclaim 14, wherein said memory device comprises a NAND-based memory card.18. The system of claim 14, wherein said first memory buffer and thefirst portion of said memory array are disposed on a same die.
 19. Thesystem of claim 14, wherein said memory device comprises a NAND-basedmemory card to receive said particular information from a memory cardcontroller.